Junction Semiconductor

Advanced Semiconductor Technology & Lithography

EUV Lithography and High-NA Innovation: Analyzed ASML EUV roadmap, including High-NA deployment scenarios and alternative sub-EUV light sources (e.g., atom lithography, FEL). Quantified productivity, cost, and power scaling implications in GAA and 3D DRAM era.Advanced Lithography Technologies: Benchmarked LPP vs. LDP, evaluated overlay/metrology tradeoffs, and explored feasibility of alternative litho paths. Created roadmap visualizations for sub-2nm patterning.

Packaging, 3D Integration & Interconnect

2.xD/3D RDL and PLP Packaging: Evaluated RDL warpage, yield modeling, HRDP vs. SAP tradeoffs on 500mm+ substrates. Reviewed materials and process flow for molded RDL and panel-level packaging.CIS Packaging and Glass Cap Integration: Assessed CSP/WLCSP reliability tradeoffs, glass capping adoption. Compared resin vs. glass transmission, height constraints, and supplier ecosystem.Polyimide and Film Materials for Packaging: Studied PI thermal stability and delamination in molding/PLP. Modeled demand trends across memory, logic, CIS, and flexible electronics.

AI Infrastructure & Optical Networking

Optical DSP and Strategy Analyzed SerDes/AEC architecture adoption by hyperscalers. Compared LPO, CPO readiness, and packaging implications for GPU cluster scaling.MCP & Inference Infrastructure Modeling Built compute/memory/network architecture stack to support GenAI workloads. Explored emerging disaggregation protocols and monitoring strategies.

Memory & HBM Stack Analysis

HBM Technology Differentiation Compared TSV pitch, stack height, process yield, and underfill reliability. Benchmarked CXL and NVLink integration scenarios for future HBM/CXL hybrid memory pooling.Non-Volatile Memory Trends (FRAM, MRAM, ReRAM) Quantified scaling, endurance, and BEOL integration issues. Evaluated FRAM maturity vs. MRAM in embedded memory market.

Foundry Strategy, Yield & Fab Modeling

Foundry Race Analysis Created node roadmap timeline to 1.4nm, comparing gate pitch, BEOL scaling, and EUV insertion points. Integrated investment and technology cadence.Fabless-to-Foundry Transfer & Foundry Economics Modeled yield, equipment cost, and risk-sharing structure across TSMC, Samsung, Intel. Explored China foundry rise and onboarding implications.

Materials & Cross-Vertical Applications

Flexible Substrates, Sensors & MEMS Integration Explored lift-off MEMS, magnetic sensors, and laser alignment integration in low-temperature process stacks. Assessed carbon thin film and specialty glass applications.SiC MOSFET & Advanced Power Packaging Evaluated Through-Dielectric Interconnect (TDI) path to cost reduction. Mapped competitive structure for SiC-based automotive and datacenter components.